For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips.
A photolithographic mask comprises geometric patterns of polygons corresponding to the circuit components to be integrated onto a wafer. The patterns used to create such masks are typically generated utilizing CAD (computer-aided design) programs via an EDA (electronic design automation) process. Most CAD programs follow a set of predetermined design rules in order to position the polygons to create functional masks. These rules are set by manufacturing process and circuit design limitations. For example, design rules define the space tolerance between circuit components (such as gates, capacitors, etc.) or interconnect lines to ensure a high device yield. The design rule limitations are typically referred to as “critical dimensions” (CD). A CD of a circuit can be defined as the smallest length of a line or trench or the smallest space between two lines or two trenches. Thus, the CD determines the overall size and density of the designed circuit.
Recently device scaling has outpaced the development of lithography systems (e.g., scanners). Patterning interconnect geometries, for example, at the 22 nm node, using a 193 nm wavelength scanner may require a nesting of every narrow drawn line to force a circuit design to an optimal pitch (e.g., having a design-rule minimum space CD for every minimum CD line) with several compliance features and a drawing of large end-to-ends in an effort to reduce the mask error enhancement factor (MEEF) of the lithographic process to an acceptable level for the lithographic technology node. The resulting increase in circuit footprint can, however, negate the benefit of scaling the CD down to the 22 nm technology node.